欢迎访问ic37.com |
会员登录 免费注册
发布采购

HYE18L512160BF-7.5 参数 Datasheet PDF下载

HYE18L512160BF-7.5图片预览
型号: HYE18L512160BF-7.5
PDF下载: 下载PDF文件 查看货源
内容描述: DRAM的移动应用512 - Mbit的移动-RAM [DRAMs for Mobile Applications 512-Mbit Mobile-RAM]
分类和应用: 存储内存集成电路动态存储器时钟
文件页数/大小: 57 页 / 2043 K
品牌: QIMONDA [ QIMONDA AG ]
 浏览型号HYE18L512160BF-7.5的Datasheet PDF文件第44页浏览型号HYE18L512160BF-7.5的Datasheet PDF文件第45页浏览型号HYE18L512160BF-7.5的Datasheet PDF文件第46页浏览型号HYE18L512160BF-7.5的Datasheet PDF文件第47页浏览型号HYE18L512160BF-7.5的Datasheet PDF文件第49页浏览型号HYE18L512160BF-7.5的Datasheet PDF文件第50页浏览型号HYE18L512160BF-7.5的Datasheet PDF文件第51页浏览型号HYE18L512160BF-7.5的Datasheet PDF文件第52页  
Data Sheet.  
HY[B/E]18L512160BF-7.5  
512-Mbit Mobile-RAM  
TABLE 25  
Electrical Characteristics  
Parameter  
Symbol  
Values  
Unit  
Notes1)  
min.  
max.  
Power Supply Voltage  
Power Supply Voltage for DQ Output Buffer VDDQ  
Input high voltage  
Input low voltage  
Output high voltage  
Output low voltage  
Input leakage current  
Output leakage current  
VDD  
1.7  
1.7  
0.8 × VDDQ  
1.95  
1.95  
DDQ + 0.3  
0.3  
0.2  
1.0  
1.5  
V
V
V
V
V
V
2)  
VIH  
VIL  
VOH  
VOL  
IIL  
V
-0.3  
V
DDQ - 0.2  
-1.0  
-1.5  
µΑ  
IOL  
µA  
1) 0 °C TC 70 °C (comm.); -25 °C TC 85 °C (ext.); All voltages referenced to VSS. VSS and VSSQ must be at same potential.  
2)  
V
IH may overshoot to VDD + 0.8 V for pulse width < 4 ns; VIL may undershoot to -0.8 V for pulse width < 4 ns.Pulse width measured at 50%  
with amplitude measured between peak voltage and DC reference level.  
3.2  
AC Characteristics  
TABLE 26  
AC Characteristics  
Parameter  
Symbol  
- 7.5  
Unit  
Notes1)2)3)4)  
min.  
max.  
Clock cycle time  
Clock frequency  
CL = 3  
CL = 2  
CL = 3  
CL = 2  
CL = 3  
CL = 2  
tCK  
fCK  
tAC  
7.5  
9.5  
133  
105  
6.0  
7.0  
7.0  
2
ns  
ns  
MHz  
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
tCK  
ns  
ns  
ns  
tCK  
tCK  
5)  
Access time from CLK  
Clock high-level width  
Clock low-level width  
tCH  
tCL  
tIS  
tIH  
tMRD  
tLZ  
2.5  
2.5  
1.5  
0.8  
2
1.0  
3.0  
2.5  
6)  
Address, data and command input setup time  
Address, data and command input hold time  
MODE REGISTER SET command period  
DQ low-impedance time from CLK  
DQ high-impedance time from CLK  
Data out hold time  
6)  
tHZ  
5)6)  
tOH  
tDQZ  
tDQW  
DQM to DQ High-Z delay (READ Commands)  
DQM write mask latency  
0
Rev. 1.22, 2006-12  
48  
01132005-06IU-IGVM  
 复制成功!