Internet Data Sheet
HY[B/I]25DC512[80/16]0D[E/F](L)
512-Mbit Double-Data-Rate SDRAM
3.2
Extended Mode Register
The Extended Mode Register controls functions beyond those controlled by the Mode Register.
%$ꢄ
ꢀ
%$ꢀ
ꢄ
$ꢄꢅ
$ꢄꢄ
$ꢄꢀ
$ꢈ
$ꢆ
$ꢂ
$ꢇ
$ꢉ
$ꢁ
$ꢊ
$ꢅ
$ꢄ
'6
Z
$ꢀ
'//
Z
02'(
Z
UHJꢃꢍDGGU
03%7ꢀꢁꢈꢀ
TABLE 11
Extended Mode Register
Field
Bits
Type1)
Description
DLL Status
DLL
0
w
0B
1B
Enabled
Disabled
DS
1
Drive Strength
0B
1B
Normal
Weak
MODE
[12:2]
Operating Mode
00000000000B Normal Operation
Notes
1. A2 must be 0 to provide compatibility with early DDR devices.
2. All other bit combinations are RESERVED.
1) w = write only register bit
Rev. 1.10, 2008-05
17
06212007-08MW-K87L
QIMONDA [ QIMONDA AG ]
