Internet Data Sheet
HY[B/I]25DC512[80/16]0D[E/F](L)
512-Mbit Double-Data-Rate SDRAM
3.1.1
Burst Type
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the burst
type and is selected via bit A3. The ordering of accesses
within a burst is determined by the burst length, the burst type
and the starting column address, as shown in Table 10.
TABLE 10
Burst Definition
Burst Length
Starting Column Address
Order of Accesses Within a Burst
A2
A1
A0
Type = Sequential
Type = Interleaved
2
4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0-1
0-1
1-0
1-0
0
0
1
1
0
0
1
1
0
0
1
1
0-1-2-3
0-1-2-3
1-2-3-0
1-0-3-2
2-3-0-1
2-3-0-1
3-0-1-2
3-2-1-0
8
0
0
0
0
1
1
1
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Notes
1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block.
3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
Rev. 1.10, 2008-05
16
06212007-08MW-K87L
QIMONDA [ QIMONDA AG ]
