Internet Data Sheet
HY[B/I]25DC512[80/16]0D[E/F](L)
512-Mbit Double-Data-Rate SDRAM
3
Functional Description
The 512-Mbit Double-Data-Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation.
3.1
Mode Register Definition
The Mode Register is used to define the specific mode of operation of the DDR SDRAM.
%$ꢄ
ꢀ
%$ꢀ
ꢀ
$ꢄꢅ
$ꢄꢄ
$ꢄꢀ
$ꢈ
$ꢆ
$ꢂ
$ꢇ
$ꢉ
&/
Z
$ꢁ
$ꢊ
%7
Z
$ꢅ
$ꢄ
%/
Z
$ꢀ
02'(
UHJꢃꢍDGGU
Z
03%7ꢀꢁꢆꢀ
TABLE 9
Mode Register Definition
Field
BL
Bits
Type1) Description
Burst Length
Note: All other bit combinations are RESERVED.
[2:0]
W
001B
010B
011B
2
4
8
BT
CL
3
Burst Type
0 Sequential
1 Interleaved
[6:4]
CAS Latency
Note: All other bit combinations are RESERVED.
010B
2
110B 2.5
011B
100B
3
4
MODE [12:7]
Operating Mode
Note: All other bit combinations are RESERVED.
000000 Normal Operation without DLL Reset
000010 Normal Operation with DLL Reset
1) W = write only register bit
Rev. 1.10, 2008-05
15
06212007-08MW-K87L
QIMONDA [ QIMONDA AG ]
