Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
Parameter
Symbol
–7
DDR266A
Unit
Note/Test
Condition1)
Min.
Max.
2)3)4)5)7)
2)3)4)5)
2)3)4)5)
Data-out low-impedance time from CK/CK
Mode register set command cycle time
DQ/DQS output hold time
tLZ
–0.75
2
+0.75
—
ns
tCK
ns
ns
ns
tMRD
tQH
tHP –tQHS
Data hold skew factor
tQHS
tRAP
tRAS
tRC
—
0.75
—
TSOPII 2)3)4)5)
2)3)4)5)
Active to Read w/AP delay
tRCD
45
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)10)
2)3)4)5)
Active to Precharge command
Active to Active/Auto-refresh command period
Active to Read or Write delay
120E+3 ns
65
—
—
—
—
ns
ns
μs
ns
tRCD
tREFI
tRFC
20
Average Periodic Refresh Interval
7.8
75
Auto-refresh to Active/Auto-refresh command
period
2)3)4)5)
Precharge command period
Read preamble
tRP
20
0.9
0.4
15
0.25
0
—
1.1
0.6
—
—
—
—
—
—
ns
tCK
tCK
ns
tCK
ns
2)3)4)5)
tRPRE
tRPST
tRRD
2)3)4)5)
Read postamble
2)3)4)5)
Active bank A to Active bank B command
Write preamble
2)3)4)5)
tWPRE
tWPRES
tWPST
tWR
2)3)4)5)11)
2)3)4)5)12)
2)3)4)5)
Write preamble setup time
Write postamble
0.4
15
1
tCK
ns
tCK
ns
tCK
Write recovery time
2)3)4)5)
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
tWTR
2)3)4)5)13)
2)3)4)5)
tXSNR
tXSRD
75
200
—
1)
VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V ; 0 °C ≤ TA ≤ 70 °C
2) Input slew rate ≥ 1 V/ns
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
7) HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VIH(ac) and VIL(ac)
.
t
.
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on tDQSS
.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
13) In all circumstances, tXSNR can be satisfied using tXSNR = tRFC,min + 1 × tCK
Rev. 1.70, 2007-11
29
03062006-PFFJ-YJY2
QIMONDA [ QIMONDA AG ]
