Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 20
DD Specification
I
–7
DDR266A
–6
–5
Unit
Note/Test Condition1)
DDR333
Typ.
DDR400B
Symbol
Typ.
Max.
Max.
Typ.
Max.
IDD0
65
80
75
90
1.5
20
15
9
78
75
90
80
100
120
110
140
4
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
×4/×8 2)3)
×16 3)
×4/×8 3)
×16 3)
3)
95
90
110
100
125
4
100
90
IDD1
90
85
110
4
105
1.6
25
115
1.7
30
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
3)
3)
3)
24
30
36
21
17
24
19
26
13
11
15
12
16
29
31
67
85
71
90
170
2.6
2.5
204
215
35
35
41
39
47
×4/×8 3)
×16 3)
×4/×8 3)
×16 3)
×4/×8 3)
×16 3)
37
37
44
42
50
IDD4R
IDD4W
78
77
90
85
100
145
105
150
245
5.0
2.5
310
340
100
83
105
81
125
95
120
90
105
205
5.0
2.5
243
255
110
185
2.7
2.5
234
255
130
220
5.0
2.5
279
310
125
205
2.8
2.5
260
285
3)4)
IDD5
IDD6
3)
low power
×4/×8 3)
×16 3)
IDD7
1) Test conditions for typical values: VDD = 2.5 V (DDR266, DDR333), VDD = 2.6 V (DDR400), TA = 25 °C, test conditions for maximum values:
DD = 2.7 V, TA = 10 °C
DD specifications are tested after the device is properly initialized and measured at 133 MHz for DDR266, 166 MHz for DDR333, and 200
MHz for DDR400.
V
2)
I
3) Input slew rate = 1 V/ns.
4) Enables on-chip refresh and address counters.
Rev. 1.70, 2007-11
31
03062006-PFFJ-YJY2
QIMONDA [ QIMONDA AG ]
