HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Functional Description
Maximum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Write
NOP
NOP
NOP
Read
NOP
Command
tWTR
BAa, COL b
BAa, COL n
Address
CL = 2
tDQSS (max)
DQS
DQ
DI a-b
DM
Minimum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Write
NOP
NOP
NOP
Read
NOP
Command
tWTR
BAa, COL n
BAa, COL b
Address
CL = 2
tDQSS (min)
DQS
DQ
DI a-b
DM
DI a-b = data in for bank a, column b.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
A non-interrupted burst is shown.
tWTR is referenced from the first positive CK edge after the last data in pair.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands may be to any bank.
Don’t Care
Figure 22 Write to Read: Non-Interrupting (CAS Latency = 2; Burst Length = 4)
Data Sheet
39
Rev. 1.21, 2004-07
02102004-TSR1-4ZWW
QIMONDA [ QIMONDA AG ]
