HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Functional Description
Maximum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Write
NOP
Write
NOP
NOP
NOP
Command
Address
BAa, COL b
BAa, COL n
tDQSS (max)
DQS
DQ
DI a-b
DI a-n
DM
Minimum DQSS
T1
T2
T3
T4
T5
T6
CK
CK
Write
NOP
Write
NOP
NOP
NOP
Command
Address
BA, COL b
BA, COL n
tDQSS (min)
DQS
DQ
DI a-b
DI a-n
DM
DI a-b = data in for bank a, column b, etc.
3 subsequent elements of data in are applied in the programmed order following DI a-b.
3 subsequent elements of data in are applied in the programmed order following DI a-n.
A non-interrupted burst is shown.
Don’t Care
Each Write command may be to any bank.
Figure 19 Write to Write (Burst Length = 4)
Data Sheet
36
Rev. 1.21, 2004-07
02102004-TSR1-4ZWW
QIMONDA [ QIMONDA AG ]
