HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Functional Description
CAS Latency = 2
CK
CK
Read
NOP
PRE
NOP
NOP
ACT
Command
tRP
BA a, COL n
BA a or all
BA a, ROW
Address
CL=2
DQS
DQ
DOa-n
CAS Latency = 2.5
CK
CK
Read
NOP
PRE
NOP
NOP
ACT
Command
tRP
BA a or all
BA a, COL n
BA a, ROW
Address
CL=2.5
DQS
DQ
DOa-n
DO a-n = data out from bank a, column n.
Cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8.
3 subsequent elements of data out appear in the programmed order following DO a-n.
Shown with nominal tAC, tDQSCK, and tDQSQ
.
Don’t Care
Figure 16 Read to Precharge: CAS Latencies (Burst Length = 4 or 8)
Data Sheet
32
Rev. 1.21, 2004-07
02102004-TSR1-4ZWW