HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Functional Description
3.3
Extended Mode Register
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional
functions include DLL enable/disable, and output drive strength selection (optional). These functions are controlled
via the bits shown in the Extended Mode Register Definition. The Extended Mode Register is programmed via the
Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored information until it is programmed
again or the device loses power. The Extended Mode Register must be loaded when all banks are idle, and the
controller must wait the specified time before initiating any subsequent operation. Violating either of these
requirements result in unspecified operation.
3.3.1
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon
returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is
automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self
refresh operation. Any time the DLL is enabled, 200 clock cycles must occur before a Read command can be
issued. This is the reason 200 clock cycles must occur before issuing a Read or Write command upon exit of self
refresh operation.
3.3.2
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. In addition this design version
supports a weak driver mode for lighter load and/or point-to-point environments which can be activated during
mode register set. I-V curves for the normal and weak drive strength are included in this document.
EMR
Extended Mode Register Definition
(BA[1:0] = 01B)
A8 A7 A6
BA1
BA0
A12
A11
A10
A9
A5
A4
A3
A2
A1
A0
0
1
OPERATING MODE
0
DS
DLL
reg. addr
w
w
w
w
Field
DLL
Bits
Type
Description
0
1
2
w
DLL Status
See Chapter 3.3.1.
0
1
Enabled
Disabled
DS
w
Drive Strength
See Chapter 3.3.2, Chapter 4.2 and Chapter 4.3.
0
1
Normal
Weak
0
w
w
0
must be set to 0
MODE
[12:3]
Operating Mode
Note:All other bit combinations are RESERVED.
0
Normal Operation
Data Sheet
20
Rev. 1.21, 2004-07
02102004-TSR1-4ZWW
QIMONDA [ QIMONDA AG ]
