HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Functional Description
3.5
Operations
3.5.1
Bank/Row Activation
Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must
be “opened” (activated). This is accomplished via the Active command and addresses A0-A13, BA0 and BA1 (see
Figure 7), which decode and select both the bank and the row to be activated. After opening a row (issuing an
Active command), a Read or Write command may be issued to that row, subject to the tRCD specification. A
subsequent Active command to a different row in the same bank can only be issued after the previous active row
has been “closed” (precharged). The minimum time interval between successive Active commands to the same
bank is defined by tRC. A subsequent Active command to another bank can be issued while the first bank is being
accessed, which results in a reduction of total row-access overhead. The minimum time interval between
successive Active commands to different banks is defined by tRRD
.
CK
CK
HIGH
CKE
CS
RAS
CAS
WE
RA = row address.
BA = bank address.
RA
BA
A0-A12
BA0, BA1
Don’t Care
Figure 7
Activating a Specific Row in a Specific Bank
CK
CK
RD/WR
ACT
NOP
ACT
NOP
NOP
NOP
NOP
Command
A0-A12
ROW
BA x
ROW
BA y
COL
BA y
BA0, BA1
tRRD
tRCD
Don’t Care
Figure 8
tRCD and tRRD Definition
Data Sheet
24
Rev. 1.21, 2004-07
02102004-TSR1-4ZWW
QIMONDA [ QIMONDA AG ]
