HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Functional Description
3.2
Mode Register Definition
The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes
the selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is
programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored information
until it is programmed again or the device loses power (except for bit A8, which is self-clearing).
Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-
A6 specify the CAS latency, and A7-A12 specify the operating mode.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these requirements results in unspecified operation.
MR
Mode Register Definition
(BA[1:0] = 00B)
A8 A7 A6
BA1
BA0
A12
A11
A10
A9
A5
A4
A3
A2
A1
A0
0
0
OPERATING MODE
CL
BT
BL
reg. addr
w
w
w
w
Field Bits Type Description
BL
[2:0]
w
Burst Length
Number of sequential bits per DQ related to one read/write command; see Chapter 3.2.1.
Note:All other bit combinations are RESERVED.
001 2
010 4
011 8
BT
CL
3
w
w
Burst Type
See Table 5 for internal address sequence of low order address bits; see Chapter 3.2.2.
0
1
Sequential
Interleaved
[6:4]
CAS Latency
Number of full clocks from read command to first data valid window; see Chapter 3.2.3.
Note:All other bit combinations are RESERVED.
010 2
011 (3.0 Optional, not covered by this data sheet)
101 2.5
110 1.5 for DDR200 components only
MODE [12:3] w
Operating Mode
Note:All other bit combinations are RESERVED.
0
Normal Operation
Data Sheet
16
Rev. 1.21, 2004-07
02102004-TSR1-4ZWW
QIMONDA [ QIMONDA AG ]
