HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM
Pin Configuration
CKE
CK
CK
CS
WE
CAS
RAS
Bank3
Bank2
Bank1
CK, CK
DLL
Mode
Registers
13
8192
Bank0
Memory
Array
Data
13
(8192 x 1024 x 8)
4
4
4
8
Sense Amplifiers
1
DQS
Generator
DQ0-DQ3,
DM
COL0
Mask
DQS
Input
Register
1
I/O Gating
DM Mask Logic
8
2
DQS
1
1
A0-A12,
BA0, BA1
Write
15
1
FIFO
1
&
8
2
8
1024
(x8)
2
Drivers
4
4
4
4
4
clk
clk
Column
Decoder
in
out
Data
10
COL0
CK,
CK
Column-Address
Counter/Latch
11
COL0
1
1
Figure 3
Notes:
Block Diagram (64Mb × 4)
1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does
not represent an actual circuit implementation.
2. DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and
DQS signals.
Data Sheet
12
Rev. 1.21, 2004-07
02102004-TSR1-4ZWW
QIMONDA [ QIMONDA AG ]
