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HYB18T1G400AF 参数 Datasheet PDF下载

HYB18T1G400AF图片预览
型号: HYB18T1G400AF
PDF下载: 下载PDF文件 查看货源
内容描述: 240引脚注册的DDR SDRAM模块 [240-Pin Registered DDR SDRAM Modules]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 40 页 / 2282 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYS72T[128/256]00xHR–[3S/3.7/5]–A  
Registered DDR2 SDRAM Modules  
Parameter  
Symbol  
DDR2–667  
Unit  
Note1)2)3)4)5)6)7)  
8)  
Min.  
Max.  
12)  
CKE minimum pulse width ( high and low pulse tCKE  
3
nCK  
width)  
1)1)  
Average clock low pulse width  
tCL.AVG  
0.48  
0.52  
tCK.AVG  
nCK  
ns  
13)14)  
Auto-Precharge write recovery + precharge time tDAL  
WR + tnRP  
Minimum time clocks remain ON after CKE  
asynchronously drops LOW  
tDELAY  
tIS + tCK .AVG  
tIH  
+
19)20)15)  
9)  
DQ and DM input hold time  
tDH.BASE  
tDIPW  
tDQSCK  
tDQSH  
175  
ps  
DQ and DM input pulse width for each input  
DQS output access time from CK / CK  
DQS input high pulse width  
0.35  
–400  
0.35  
0.35  
tCK.AVG  
ps  
+400  
tCK.AVG  
tCK.AVG  
ps  
DQS input low pulse width  
tDQSL  
16)  
17)  
DQS-DQ skew for DQS & associated DQ signals tDQSQ  
240  
+0.25  
DQS latching rising transition to associated clock tDQSS  
–0.25  
tCK.AVG  
edges  
18)19)20)  
17)  
DQ and DM input setup time  
DQS falling edge hold time from CK  
DQS falling edge to CK setup time  
CK half pulse width  
tDS.BASE  
100  
0.2  
0.2  
––  
__  
ps  
tDSH  
tDSS  
tHP  
tCK.AVG  
tCK.AVG  
ps  
17)  
21)  
Min(tCH.ABS  
,
tCL.ABS  
)
9)22)  
Data-out high-impedance time from CK / CK  
Address and control input hold time  
tHZ  
tAC.MAX  
ps  
25)23)  
tIH.BASE  
275  
0.6  
ps  
Control & address input pulse width for each input tIPW  
tCK.AVG  
ps  
24)25)  
9)22)  
9)22)  
1)  
Address and control input setup time  
DQ low impedance time from CK/CK  
DQS/DQS low-impedance time from CK / CK  
MRS command to ODT update delay  
Mode register set command cycle time  
OCD drive mode output delay  
DQ/DQS output hold time from DQS  
DQ hold skew factor  
tIS.BASE  
200  
tLZ.DQ  
tLZ.DQS  
tMOD  
tMRD  
tOIT  
2 × tAC.MIN  
tAC.MAX  
tAC.MAX  
12  
ps  
tAC.MIN  
ps  
0
2
0
ns  
nCK  
ns  
1)  
12  
26)  
tQH  
t
HP tQHS  
ps  
27)  
tQHS  
340  
1.1  
0.6  
ps  
28)29)  
28)30)  
31)  
Read preamble  
tRPRE  
tRPST  
tRTP  
0.9  
0.4  
7.5  
0.35  
0.4  
15  
tCK.AVG  
tCK.AVG  
ns  
Read postamble  
Internal Read to Precharge command delay  
Write preamble  
tWPRE  
tWPST  
tWR  
tCK.AVG  
tCK.AVG  
ns  
Write postamble  
0.6  
31)  
Write recovery time  
31)32)  
Internal write to read command delay  
Exit power down to read command  
tWTR  
tXARD  
7.5  
2
ns  
nCK  
nCK  
Exit active power-down mode to read command tXARDS  
7 – AL  
(slow exit, lower power)  
Rev. 1.4, 2007-02  
17  
03062006-GD6J-14FP  
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