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HYB18T1G400AF 参数 Datasheet PDF下载

HYB18T1G400AF图片预览
型号: HYB18T1G400AF
PDF下载: 下载PDF文件 查看货源
内容描述: 240引脚注册的DDR SDRAM模块 [240-Pin Registered DDR SDRAM Modules]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 40 页 / 2282 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYS72T[128/256]00xHR–[3S/3.7/5]–A  
Registered DDR2 SDRAM Modules  
TABLE 13  
DRAM Component Timing Parameter by Speed Grade - DDR2–533  
Parameter  
Symbol  
DDR2–533  
Unit  
Note1)2)3)4)5)  
6)7)  
Min.  
Max.  
DQ output access time from CK / CK  
CAS A to CAS B command period  
CK, CK high-level width  
tAC  
–500  
2
+500  
ps  
tCCD  
tCH  
tCKE  
tCL  
tCK  
tCK  
tCK  
tCK  
tCK  
0.45  
3
0.55  
CKE minimum high and low pulse width  
CK, CK low-level width  
0.45  
WR + tRP  
0.55  
8)18)  
9)  
Auto-Precharge write recovery + precharge  
time  
tDAL  
Minimum time clocks remain ON after CKE  
asynchronously drops LOW  
tDELAY  
tIS + tCK + tIH  
225  
––  
––  
ns  
ps  
ps  
10)  
11)  
DQ and DM input hold time (differential data  
strobe)  
t
t
DH(base)  
DQ and DM input hold time (single ended data  
strobe)  
DH1(base)  
–25  
DQ and DM input pulse width (each input)  
DQS output access time from CK / CK  
tDIPW  
0.35  
–450  
0.35  
tCK  
ps  
tCK  
ps  
tDQSCK  
+450  
DQS input low (high) pulse width (write cycle) tDQSL,H  
11)  
DQS-DQ skew (for DQS & associated DQ  
signals)  
tDQSQ  
300  
Write command to 1st DQS latching transition tDQSS  
– 0.25  
100  
+ 0.25  
tCK  
11)  
11)  
DQ and DM input setup time (differential data  
strobe)  
t
DS(base)  
ps  
DQ and DM input setup time (single ended data tDS1(base)  
strobe)  
–25  
0.2  
ps  
DQS falling edge hold time from CK (write  
cycle)  
tDSH  
tCK  
tCK  
DQS falling edge to CK setup time (write cycle) tDSS  
0.2  
12)  
13)  
11)  
Clock half period  
tHP  
MIN. (tCL, tCH)  
Data-out high-impedance time from CK / CK  
Address and control input hold time  
tHZ  
tAC.MAX  
ps  
ps  
tCK  
tIH(base)  
tIPW  
375  
0.6  
Address and control input pulse width  
(each input)  
11)  
14)  
14)  
Address and control input setup time  
DQ low-impedance time from CK / CK  
DQS low-impedance from CK / CK  
Mode register set command cycle time  
OCD drive mode output delay  
tIS(base)  
tLZ(DQ)  
tLZ(DQS)  
tMRD  
250  
ps  
ps  
ps  
tCK  
ns  
ps  
µs  
2 × tAC.MIN  
tAC.MAX  
tAC.MAX  
tAC.MIN  
2
0
tOIT  
12  
Data output hold time from DQS  
Data hold skew factor  
tQH  
t
HP tQHS  
tQHS  
400  
7.8  
14)15)  
Average periodic refresh Interval  
tREFI  
Rev. 1.4, 2007-02  
21  
03062006-GD6J-14FP  
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