Internet Data Sheet
HYS72T[128/256]00xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
FIGURE 3
Differential input waveform timing - tDS and tDS
'46ꢀ
'46ꢀ ꢀ
W'+ꢀ
W'+ꢀ
W'6ꢀ ꢀ
W'6ꢀ
9'ꢀ '4ꢀ ꢀ
9,ꢀ+ꢐDFꢀ ꢑꢀꢀPLQꢀ ꢀ
9,ꢀ+ꢐGFꢀ ꢑꢀꢀPLQꢀ ꢀ
95ꢀ ()ꢐGFꢑꢀ
9,ꢀ/ꢀꢐꢀGFꢀ ꢑꢀꢀPD[ꢀ ꢀ
9,ꢀ/ꢀꢐꢀDFꢀ ꢑꢀꢀPD[ꢀ ꢀ
96ꢀ 6ꢀ
FIGURE 4
Differential input waveform timing - tlS and tlH
&.ꢀ
&.ꢀ
W,+ꢀ ꢀ
W,+ꢀ ꢀ
W,6ꢀ
W,6ꢀ ꢀ
9'ꢀ '4ꢀ ꢀ
9,ꢀ+ꢐꢀDFꢀ ꢑꢀꢀPLQꢀ
9,ꢀ+ꢐꢀGFꢀ ꢑꢀꢀPLQꢀ
95ꢀ ()ꢐGFꢑꢀ
9,ꢀ/ꢀꢐGFꢀ ꢑꢀꢀPD[ꢀ ꢀ
9,ꢀ/ꢀꢐDFꢀ ꢑꢀꢀPD[ꢀ ꢀ
96ꢀ 6ꢀ
Rev. 1.4, 2007-02
20
03062006-GD6J-14FP