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HYB18T1G400AF 参数 Datasheet PDF下载

HYB18T1G400AF图片预览
型号: HYB18T1G400AF
PDF下载: 下载PDF文件 查看货源
内容描述: 240引脚注册的DDR SDRAM模块 [240-Pin Registered DDR SDRAM Modules]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 40 页 / 2282 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYS72T[128/256]00xHR–[3S/3.7/5]–A  
Registered DDR2 SDRAM Modules  
3.2  
DC Operating Conditions  
TABLE 9  
Operating Conditions  
Parameter  
Symbol  
Values  
Min.  
Unit  
Note  
Max.  
1)  
DIMM Module Operating Temperature Range (ambient)  
DRAM Component Case Temperature Range  
Storage Temperature  
TOPR  
TCASE  
TSTG  
PBar  
0
+55  
+95  
+100  
+105  
90  
°C  
°C  
°C  
kPa  
%
2)3)4)5)  
0
–55  
+69  
10  
6)  
Barometric Pressure (operating & storage)  
Operating Humidity (relative)  
HOPR  
1) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by  
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50 %  
2) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.  
3) Within the DRAM Component Case Temperature range all DRAM specification will be supported.  
4) Above 85 °C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.  
5) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85 °C case  
temperature before initiating self-refresh operation.  
6) Up to 3000 m  
TABLE 10  
Supply Voltage Levels and DC Operating Conditions  
Parameter  
Symbol  
Values  
Min.  
Unit  
Note  
Typ.  
Max.  
Device Supply Voltage  
Output Supply Voltage  
Input Reference Voltage  
SPD Supply Voltage  
VDD  
1.7  
1.8  
1.9  
V
1)  
2)  
VDDQ  
VREF  
1.7  
1.8  
1.9  
V
0.49 × VDDQ  
0.5 × VDDQ  
0.51 × VDDQ  
V
VDDSPD  
VIH(DC)  
VIL (DC  
IL  
1.7  
3.6  
V
DC Input Logic High  
VREF + 0.125  
V
V
5
DDQ + 0.3  
V
DC Input Logic Low  
)
– 0.30  
– 5  
REF – 0.125  
V
3)  
In / Output Leakage Current  
µA  
1) Under all conditions, VDDQ must be less than or equal to VDD  
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise in VDDQ  
3) Input voltage for any connector pin under test of 0 V VIN VDDQ + 0.3 V; all other pins at 0 V. Current is per pin  
.
Rev. 1.4, 2007-02  
15  
03062006-GD6J-14FP  
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