HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
2
Pin Configuration
2.1
Pin Configuration
The pin configuration of a DDR2 SDRAM is listed by function in Table 6. The abbreviations used in the Pin# and
Buffer Type columns are explained in Table 7 and Table 8 respectively. The pin numbering for the FBGA package
is depicted in Figure 1 for ×4, Figure 2 for ×8 and Figure 3 for ×16.
Table 6
Pin Configuration of DDR2 SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
Clock Signals ×4/×8 organizations
E8
F8
F2
CK
I
I
I
SSTL
SSTL
SSTL
Clock Signal CK, Complementary Clock Signal CK
Clock Enable
CK
CKE
Clock Signals ×16 organization
J8
CK
I
I
I
SSTL
SSTL
SSTL
Clock Signal CK, Complementary Clock Signal CK
Note: See functional description in x4/x8 organization
Clock Enable
K8
K2
CK
CKE
Note: See functional description in x4/x8 organization
Control Signals ×4/×8 organizations
F7
G7
F3
G8
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
CS
Chip Select
Control Signals ×16 organization
K7
L7
K3
L8
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
CS
Chip Select
Address Signals ×4/×8 organizations
G2
G3
BA0
BA1
I
I
SSTL
SSTL
Bank Address Bus 1:0
Internet Data Sheet
7
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
QIMONDA [ QIMONDA AG ]
