HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 4
Performance for DDR2–400B
Product Type Speed Code
Speed Grade
–5
Units
DDR2–400B 3–3–3
—
max. Clock Frequency
@CL5
@CL4
@CL3
fCK5
fCK4
fCK3
200
200
200
MHz
MHz
MHz
ns
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
tRCD 15
tRP 15
tRAS 40
tRC 55
ns
ns
ns
1.2
Description
The 512-Mb DDR2 DRAM is a high-speed Double- Inputs are latched at the cross point of differential
Data-Rate-Two CMOS DRAM device containing clocks (CK rising and CK falling). All I/Os are
536,870,912 bits and internally configured as a quad- synchronized with a single ended DQS or differential
bank DRAM. The 512-Mb device is organized as either DQS-DQS pair in a source synchronous fashion.
32 Mbit × 4 I/O ×4 banks, 16 Mbit ×8 I/O × 4 banks or
8 Mbit ×16 I/O ×4 banks chip. These devices achieve
high speed transfer rates starting at 400 Mb/sec/pin for
general applications. See Table 1 to Table 4 for
performance figures.
A 16-bit address bus for ×4 and ×8 organized
components and a 15-bit address bus for ×16
components is used to convey row, column and bank
address information in a RAS-CAS multiplexing style.
The DDR2 device operates with a 1.8 V ± 0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is
provided along with various power-saving power-down
modes.
The device is designed to comply with all DDR2 DRAM
key features:
1. Posted CAS with additive latency,
2. Write latency = read latency - 1,
The functionality described and the timing
specifications included in this data sheet are for the
DLL Enabled mode of operation.
3. Normal and weak strength data-output driver,
4. Off-Chip Driver (OCD) impedance adjustment
5. On-Die Termination (ODT) function.
The DDR2 SDRAM is available in PG-TFBGA
package.
All of the control and address inputs are synchronized
with a pair of externally supplied differential clocks.
Internet Data Sheet
5
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
QIMONDA [ QIMONDA AG ]
