HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 43
Timing Parameter by Speed Grade - DDR2-533
Parameter
Symbol
DDR2–533
Unit Note1)2)3)4)
5)6)
Min.
–500
2
Max.
+500
—
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
tAC
ps
—
—
—
—
tCCD
tCH
tCKE
tCL
tCK
tCK
tCK
tCK
tCK
0.45
3
0.55
—
CKE minimum high and low pulse width
CK, CK low-level width
0.45
WR + tRP
0.55
—
—
7)
Auto-Precharge write recovery +
precharge time
tDAL
8)
Minimum time clocks remain ON after CKE tDELAY
asynchronously drops LOW
tIS + tCK + tIH
225
––
––
—
ns
ps
ps
DQ and DM input hold time (differential
data strobe)
tDH(base)
DH1(base)
—
—
DQ and DM input hold time (single ended
data strobe)
t
–25
DQ and DM input pulse width (each input) tDIPW
0.35
–450
0.35
—
tCK
ps
—
—
—
DQS output access time from CK / CK
tDQSCK
tDQSL,H
+450
—
DQS input low (high) pulse width (write
cycle)
tCK
9)
DQS-DQ skew (for DQS & associated DQ tDQSQ
signals)
—
300
+ 0.25
—
ps
tCK
ps
ps
tCK
tCK
Write command to 1st DQS latching
transition
tDQSS
– 0.25
100
–25
0.2
—
—
—
—
—
DQ and DM input setup time (differential
data strobe)
tDS(base)
DQ and DM input setup time (single ended tDS1(base)
data strobe)
—
DQS falling edge hold time from CK (write tDSH
cycle)
—
DQS falling edge to CK setup time (write tDSS
0.2
—
cycle)
10)
11)
Clock half period
tHP
MIN. (tCL, tCH)
—
ps
Data-out high-impedance time from CK / tHZ
—
tAC.MAX
CK
Address and control input hold time
tIH(base)
375
0.6
—
—
ps
—
—
Address and control input pulse width
(each input)
tIPW
tCK
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
250
—
ps
ps
ps
tCK
ns
—
—
—
—
—
—
—
2 × tAC.MIN
tAC.MAX
tAC.MAX
—
tAC.MIN
2
0
tOIT
12
Data output hold time from DQS
tQH
t
HP –tQHS
—
Internet Data Sheet
44
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
QIMONDA [ QIMONDA AG ]
