HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 42
Timing Parameter by Speed Grade - DDR2–667 (cont’d)
Parameter
Symbol
DDR2–667
Unit
Note1)2)3)4)5)
6)
Min.
Max.
9)
DQS-DQ skew (for DQS & associated DQ
signals)
tDQSQ
tDQSS
—
240
ps
tCK
ps
ps
tCK
tCK
Write command to 1st DQS latching
transition
– 0.25
100
––
+ 0.25
—
—
—
—
—
—
DQ and DM input setup time (differential data tDS(base)
strobe)
DQ and DM input setup time (single ended
data strobe)
t
DS1(base)
—
DQS falling edge hold time from CK (write
cycle)
tDSH
tDSS
tHP
0.2
—
DQS falling edge to CK setup time (write
cycle)
0.2
—
10)
11)
Clock half period
MIN. (tCL, tCH)
—
ps
ps
tCK
Data-out high-impedance time from CK / CK tHZ
—
tAC.MAX
Address and control input hold time
tIH(base)
275
0.6
—
—
—
Address and control input pulse width
(each input)
tIPW
—
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
200
—
ps
ps
ps
tCK
ns
—
ps
µs
µs
ns
—
—
—
—
—
—
2 × tAC.MIN
tAC.MAX
tAC.MAX
—
tAC.MIN
2
0
tOIT
12
Data output hold time from DQS
Data hold skew factor
tQH
t
HPQ – tQHS
—
tQHS
—
—
340
7.8
—
12)13)
Average periodic refresh Interval
tREFI
14)
15)
—
3.9
Auto-Refresh to Active/Auto-Refresh
command period
tRFC
105
—
16)
Precharge-All (4 banks) command period
Read preamble
tRP
tRP
—
ns
tCK
tCK
ns
ns
ns
tCK
tCK
ns
tRPRE
tRPST
tRRD
0.9
1.1
0.60
—
—
Read postamble
0.40
7.5
—
17)
Active bank A to Active bank B command
period
10
—
—
—
Internal Read to Precharge command delay tRTP
7.5
—
Write preamble
Write postamble
tWPRE
tWPST
tWR
0.35 x tCK
0.40
15
—
—
18)
0.60
—
Write recovery time for write without Auto-
Precharge
—
19)
Write recovery time for write with Auto-
Precharge
WR
t
WR/tCK
—
—
tCK
20)
Internal Write to Read command delay
tWTR
7.5
ns
Internet Data Sheet
42
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
QIMONDA [ QIMONDA AG ]
