HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 44
Timing Parameter by Speed Grade - DDR2-400
Parameter
Symbol
DDR2–400
Unit Note1)2)3)4)5)
6)
Min.
—
Max.
450
7.8
Data hold skew factor
tQHS
tREFI
ps
µs
µs
ns
—
12)13)
Average periodic refresh Interval
—
14)
15)
—
3.9
Auto-Refresh to Active/Auto-Refresh
command period
tRFC
105
—
16)
Precharge-All (4 banks) command period tRP
tRP
0.9
0.40
7.5
10
—
ns
tCK
tCK
ns
ns
ns
Read preamble
Read postamble
tRPRE
tRPST
1.1
0.60
—
—
—
17)
Active bank A to Active bank B command tRRD
period
—
—
—
Internal Read to Precharge command
delay
tRTP
7.5
—
Write preamble
Write postamble
tWPRE
tWPST
0.25 x tCK
0.40
—
tCK
tCK
ns
—
18)
0.60
—
Write recovery time for write without Auto- tWR
15
Precharge
19)
Write recovery time for write with Auto-
Precharge
WR
t
WR/tCK
—
tCK
20)
21)
Internal Write to Read command delay
tWTR
10
2
—
—
ns
Exit power down to any valid command
(other than NOP or Deselect)
tXARD
tCK
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
tXP
6 – AL
2
—
—
tCK
tCK
—
—
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit Self-Refresh to non-Read command tXSNR
Exit Self-Refresh to Read command tXSRD
1) VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1 V. See notes
t
RFC +10
—
—
ns
—
—
200
tCK
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
powered down and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross.
The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
6) The output timing reference voltage level is VTT.
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period.
WR refers to the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock
frequency change during power-down, a specific procedure is required.
9) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle.
10) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
this value can be greater than the minimum specification limits for tCL and tCH).
Internet Data Sheet
48
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
QIMONDA [ QIMONDA AG ]
