HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period.
WR refers to the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock
frequency change during power-down, a specific procedure is required.
9) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle.
10) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
this value can be greater than the minimum specification limits for tCL and tCH).
11) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is
no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as
valid data transitions.These parameters are verified by design and characterization, but not subject to production test.
12) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range
between 85 °C and 95 °C.
13) 0 °C≤ TCASE ≤ 85 °C
14) 85 °C < TCASE ≤ 95 °C
15) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
16) tRP(A) for a Precharge-All command for an 8 bank device is equal to tRP + 1tCK, where tRP are the values for a single bank
precharge.
17) The tRRD timing parameter depends on the page size of the DRAM organization. See Chapter 1
18) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter,
but system performance (bus turnaround) degrades accordingly.
19) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where
WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not
already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR
parameter stored in the MRS.
20) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard
active power-down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down
mode” (MR, A12 =”1”) a slow power-down exit timing tXARDS has to be satisfied.
Table 42
Timing Parameter by Speed Grade - DDR2–667
Parameter
Symbol
DDR2–667
Unit
Note1)2)3)4)5)
6)
Min.
–450
2
Max.
+450
—
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
tAC
ps
—
—
—
—
tCCD
tCH
tCKE
tCL
tCK
tCK
tCK
tCK
tCK
0.45
3
0.55
—
CKE minimum high and low pulse width
CK, CK low-level width
0.45
WR + tRP
0.55
—
—
7)
Auto-Precharge write recovery + precharge tDAL
time
8)
Minimum time clocks remain ON after CKE tDELAY
asynchronously drops LOW
tIS + tCK + tIH
—
––
—
ns
ps
ps
DQ and DM input hold time (differential data tDH(base)
strobe)
175
––
—
—
DQ and DM input hold time (single ended
data strobe)
tDH1(base)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
tDIPW
0.35
–400
0.35
—
tCK
ps
—
—
—
tDQSCK
+400
—
DQS input low (high) pulse width (write cycle) tDQSL,H
tCK
Internet Data Sheet
41
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
QIMONDA [ QIMONDA AG ]
