HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
7.2
AC Timing Parameters
List of Timing Parameters Tables.
•
•
•
•
Table 41 “Timing Parameter by Speed Grade - DDR2–800” on Page 39
Table 42 “Timing Parameter by Speed Grade - DDR2–667” on Page 41
Table 43 “Timing Parameter by Speed Grade - DDR2-533” on Page 44
Table 44 “Timing Parameter by Speed Grade - DDR2-400” on Page 47
Table 41
Timing Parameter by Speed Grade - DDR2–800
Symbol
Parameter
DDR2–800
Unit Note1)2)3)4)5)
6)
Min.
–400
2
Max.
+400
—
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
tAC
ps
—
—
—
—
tCCD
tCH
tCKE
tCL
tCK
tCK
tCK
tCK
tCK
0.45
3
0.55
—
CKE minimum high and low pulse width
CK, CK low-level width
0.45
WR + tRP
0.55
—
—
7)
Auto-Precharge write recovery + precharge tDAL
time
8)
Minimum time clocks remain ON after CKE tDELAY
asynchronously drops LOW
tIS + tCK + tIH ––
ns
ps
ps
DQ and DM input hold time (differential
data strobe)
tDH(base)
tDH1(base)
125
––
––
—
—
—
DQ and DM input hold time (single ended
data strobe)
DQ and DM input pulse width (each input) tDIPW
0.35
–350
0.35
—
tCK
ps
—
—
—
DQS output access time from CK / CK
tDQSCK
tDQSL,H
+350
—
DQS input low (high) pulse width (write
cycle)
tCK
9)
DQS-DQ skew (for DQS & associated DQ tDQSQ
signals)
—
200
+ 0.25
—
ps
tCK
ps
ps
tCK
tCK
Write command to 1st DQS latching
transition
tDQSS
– 0.25
50
—
—
—
—
—
DQ and DM input setup time (differential
data strobe)
tDS(base)
DQ and DM input setup time (single ended tDS1(base)
data strobe)
––
—
DQS falling edge hold time from CK (write tDSH
cycle)
0.2
0.2
—
DQS falling edge to CK setup time (write
cycle)
tDSS
—
10)
11)
Clock half period
tHP
tHZ
MIN. (tCL, tCH)
—
ps
Data-out high-impedance time from CK /
CK
—
tAC.MAX
Address and control input hold time
tIH(base)
250
0.6
—
—
ps
—
—
Address and control input pulse width
(each input)
tIPW
tCK
Internet Data Sheet
39
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
QIMONDA [ QIMONDA AG ]
