HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
7
Timing Characteristics
This chapter contains speed grade definition, AC timing parameter and ODT tables.
7.1
Speed Grade Definitions
All Speed grades faster than DDR2-DDR400B comply with DDR2-DDR400B timing specifications(tCK = 5ns with
RAS = 40ns).
List of Speed Grade Definition tables:
t
•
•
•
•
Table 37 “Speed Grade Definition Speed Bins DDR2–800” on Page 36
Table 38 “Speed Grade Definition Speed Bins for DDR2–667” on Page 37
Table 39 “Speed Grade Definition Speed Bins for DDR2–533C” on Page 37
Table 40 “Speed Grade Definition Speed Bins for DDR2–400B” on Page 38
Table 37
Speed Grade Definition Speed Bins DDR2–800
Speed Grade
DDR2–800D
–2.5F
DDR2–800E
–2.5
Unit
Note
IFX Sort Name
CAS-RCD-RP latencies
Parameter
5–5–5
6–6–6
tCK
—
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
tCK
Min.
5
Max.
Min.
5
Max.
1)2)3)4)
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
@ CL = 6
8
8
tCK
3.75
2.5
8
3.75
3
8
—
—
tCK
8
8
tCK
2.5
8
2.5
45
60
15
15
8
—
5)
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRC
tRCD
tRP
45
70000
—
70000
—
57.5
12.5
12.5
—
—
—
—
—
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS,
RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
equal to 9 x tREFI
.
Internet Data Sheet
36
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
QIMONDA [ QIMONDA AG ]
