HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
6
Specifications and Conditions
Table 34
IDD Measurement Conditions
Parameter
Symbol Note
1)2)3)4)
Operating Current - One bank Active - Precharge
CK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), CKE is HIGH, CS is HIGH between valid
IDD0
5)6)
t
commands. Address and control inputs are switching; Databus inputs are switching.
Operating Current - One bank Active - Read - Precharge
IDD1
I
OUT = 0 mA, BL = 4, tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), tRCD = tRCD(IDD), AL = 0, CL =
CL(IDD); CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are
switching; Databus inputs are switching.
Precharge Power-Down Current
IDD2P
All banks idle; CKE is LOW; tCK = tCK(IDD);Other control and address inputs are stable; Data bus
inputs are floating.
Precharge Standby Current
IDD2N
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are
switching, Data bus inputs are switching.
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are
stable, Data bus inputs are floating.
IDD2Q
IDD3P(0)
IDD3P(1)
IDD3N
Active Power-Down Current
All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable; Data bus
inputs are floating. MRS A12 bit is set to “0” (Fast Power-down Exit).
Active Power-Down Current
All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable, Data bus
inputs are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);
Active Standby Current
All banks open; tCK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between
valid commands. Address inputs are switching; Data Bus inputs are switching;
Operating Current
IDD4R
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD)
;
t
RAS = tRAS.MAX.(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address
inputs are switching; Data Bus inputs are switching; IOUT = 0 mA.
Operating Current
IDD4W
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD)
;
t
RAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address
inputs are switching; Data Bus inputs are switching;
Burst Refresh Current
IDD5B
t
CK = tCK(IDD), Refresh command every tRFC = tRFC(IDD) interval, CKE is HIGH, CS is HIGH between
valid commands, Other control and address inputs are switching, Data bus inputs are switching.
Distributed Refresh Current
IDD5D
t
CK = tCK(IDD), Refresh command every tREFI = 7.8 µs interval, CKE is LOW and CS is HIGH
between valid commands, Other control and address inputs are switching, Data bus inputs are
switching.
Internet Data Sheet
33
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
QIMONDA [ QIMONDA AG ]
