欢迎访问ic37.com |
会员登录 免费注册
发布采购

HYB18T512400BF-5 参数 Datasheet PDF下载

HYB18T512400BF-5图片预览
型号: HYB18T512400BF-5
PDF下载: 下载PDF文件 查看货源
内容描述: 512兆位双数据速率 - 双SDRAM的 [512-Mbit Double-Data-Rate-Two SDRAM]
分类和应用: 内存集成电路动态存储器双倍数据速率
文件页数/大小: 57 页 / 2915 K
品牌: QIMONDA [ QIMONDA AG ]
 浏览型号HYB18T512400BF-5的Datasheet PDF文件第23页浏览型号HYB18T512400BF-5的Datasheet PDF文件第24页浏览型号HYB18T512400BF-5的Datasheet PDF文件第25页浏览型号HYB18T512400BF-5的Datasheet PDF文件第26页浏览型号HYB18T512400BF-5的Datasheet PDF文件第28页浏览型号HYB18T512400BF-5的Datasheet PDF文件第29页浏览型号HYB18T512400BF-5的Datasheet PDF文件第30页浏览型号HYB18T512400BF-5的Datasheet PDF文件第31页  
HYB18T512xxxBF–[2.5…5]  
512-Mbit Double-Data-Rate-Two SDRAM  
5.3  
DC & AC Characteristics  
DDR2 SDRAM pin timing are specified for either single relative to the rising or falling edges of DQS crossing at  
ended or differential mode depending on the setting of REF. In differential mode, these timing relationships  
V
the EMRS(1) “Enable DQS” mode bit; timing are measured relative to the crosspoint of DQS and its  
advantages of differential mode are realized in system complement, DQS. This distinction in timing methods is  
design. The method by which the DDR2 SDRAM pin verified by design and characterization but not subject  
timing are measured is mode dependent. In single to production test. In single ended mode, the DQS (and  
ended mode, timing relationships are measured RDQS) signals are internally disabled and don’t care.  
Table 24  
Symbol  
DC & AC Logic Input Levels for DDR2-667 and DDR2-800  
Parameter  
DDR2-667, DDR2-800  
Min.  
Units  
Max.  
VIH(dc)  
VIL(dc)  
VIH(ac)  
VIL(ac)  
DC input logic high  
DC input low  
V
REF + 0.125  
V
V
DDQ + 0.3  
REF – 0.125  
V
V
V
V
–0.3  
AC input logic high  
AC input low  
V
REF + 0.200  
VREF – 0.200  
Table 25  
Symbol  
DC & AC Logic Input Levels for DDR2-533 and DDR2-400  
Parameter  
DDR2-533, DDR2-400  
Min.  
Units  
Max.  
VIH(dc)  
VIL(dc)  
VIH(ac)  
VIL(ac)  
DC input logic high  
DC input low  
V
REF + 0.125  
V
V
DDQ + 0.3  
V
V
V
V
–0.3  
REF - 0.125  
AC input logic high  
AC input low  
V
REF + 0.250  
VREF - 0.250  
Table 26  
Symbol  
VREF  
Single-ended AC Input Test Conditions  
Condition  
Value  
Unit  
V
Note  
1)  
Input reference voltage  
0.5 x VDDQ  
1.0  
VSWING.MAX  
SLEW  
Input signal maximum peak to peak swing  
Input signal minimum Slew Rate  
V
2)3)  
1.0  
V / ns  
1) Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.  
2) The input signal minimum Slew Rate is to be maintained over the range from VIH(ac).MIN to VREF for rising edges and the  
range from VREF to VIL(ac).MAX for falling edges as shown in Figure 4  
3) AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac)  
on the negative transitions.  
Internet Data Sheet  
27  
Rev. 1.05, 2007-01  
03292006-YBYM-WG0Z  
 复制成功!