HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
4
Truth Tables
Table 16
Function
Command Truth Table
CKE
CS RAS CAS WE BA0 A[13:11] A10 A[9:0] Note1)2)3)
BA1
Previous Current
Cycle
Cycle
4)5)
(Extended) Mode
Register Set
H
H
L
L
L
L
BA
OP Code
Auto-Refresh
H
H
L
H
L
L
L
H
L
L
L
L
L
L
L
L
H
H
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
—
6)
Self-Refresh Entry
Self-Refresh Exit
L
L
7)
H
X
H
L
X
H
H
H
H
L
Single Bank Precharge H
H
H
H
H
H
BA
X
X
X
L
X
X
—
—
Precharge all Banks
Bank Activate
Write
H
H
H
H
L
L
H
L
H
L
BA
BA
BA
Row Address
—
8)
H
H
Column
Column
L
Column
Write with Auto-
Precharge
L
L
H
Column —
Read
H
H
H
H
L
L
H
H
L
L
H
H
BA
BA
Column
Column
L
Column —
Column —
Read with Auto-
Precharge
H
No Operation
H
H
H
X
X
L
L
H
X
X
H
X
H
H
X
X
H
X
H
H
X
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
—
Device Deselect
Power Down Entry
H
H
L
9)
Power Down Exit
L
H
H
L
X
X
X
X
—
1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
2) “X” means “H or L (but a defined logic level)”.
3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must
be powered down and then restarted through the specified initialization sequence before normal operation can continue.
4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock.
5) Bank addresses BA[1:0] determine which bank is to be operated upon. For (E)MRS BA[1:0] selects an (Extended) Mode
Register.
6) VREF must be maintained during Self Refresh operation.
7) Self Refresh Exit is asynchronous.
8) Burst reads or writes at BL = 4 cannot be terminated.
9) The Power Down Mode does not perform any refresh operations.
Internet Data Sheet
23
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
QIMONDA [ QIMONDA AG ]
