HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
5.4
Output Buffer Characteristics
Table 28
Symbol
IOH
SSTL_18 Output DC Current Drive
Parameter
SSTL_18
–13.4
Unit
mA
mA
Note
1)2)
Output Minimum Source DC Current
Output Minimum Sink DC Current
3)
IOL
13.4
1) VDDQ = 1.7 V; VOUT = 1.42 V. (VOUT–VDDQ) / IOH must be less than 21 Ohm for values of VOUT between VDDQ and
DDQ – 280 mV.
V
2) The values of IOH(dc) and IOL(dc) are based on the conditions given in and . They are used to test drive current capability to
ensure VIH.MIN. plus a noise margin and VIL.MAX minus a noise margin are delivered to an SSTL_18 receiver. The actual
current values are derived by shifting the desired driver operating points along 21 Ohm load line to define a convenient
current for measurement.
3) VDDQ = 1.7 V; VOUT = 280 mV. VOUT / IOL must be less than 21 Ohm for values of VOUT between 0 V and 280 mV.
Table 29
Symbol
VOH
SSTL_18 Output AC Test Conditions
Parameter
SSTL_18
Unit
V
Note
1)
Minimum Required Output Pull-up
Maximum Required Output Pull-down
Output Timing Measurement Reference Level
VTT + 0.603
VTT – 0.603
0.5 × VDDQ
VOL
V
—
—
VOTR
V
1) SSTL_18 test load for VOH and VOL is different from the referenced load. The SSTL_18 test load has a 20 Ohm series
resistor additionally to the 25 Ohm termination resistor into VTT. The SSTL_18 definition assumes that ± 335 mV must be
developed across the effectively 25 Ohm termination resistor (13.4 mA × 25 Ohm = 335 mV). With an additional series
resistor of 20 Ohm this translates into a minimum requirement of 603 mV swing relative to VTT, at the ouput device (13.4
mA × 45 Ohm = 603 mV).
Table 30
OCD Default Characteristics
Description
Symbol
Min.
—
0
Nominal
Max.
Unit
Note
1)2)
—
—
—
Output Impedance
Ohms
Ohms
Ohms
3)
4)
Pull-up / Pull down mismatch
—
—
4
Output Impedance step size
for OCD calibration
0
1.5
5)6)7)
SOUT
Output Slew Rate
1.5
—
5.0
V / ns
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) Impedance measurement condition for output source dc current: VDDQ = 1.7 V, VOUT = 1420 mV;
(VOUT–VDDQ) / IOH must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ – 280 mV. Impedance
measurement condition for output sink dc current: VDDQ = 1.7 V; VOUT = –280 mV; VOUT / IOL must be less than 23.4 Ohms
for values of VOUT between 0 V and 280 mV.
3) Mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage.
4) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and
represents only the DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18
± 0.75 Ohms under nominal conditions.
5) The absolute value of the Slew Rate as measured from DC to DC is equal to or greater than the Slew Rate as measured
from AC to AC. This is verified by design and characterization but not subject to production test.
6) Timing skew due to DRAM output Slew Rate mis-match between DQS / DQS and associated DQ’s is included in tDQSQ and
t
QHS specification.
7) DRAM output Slew Rate specification applies to 400, 533 and 667 MT/s speed bins.
Internet Data Sheet
29
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
QIMONDA [ QIMONDA AG ]
