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HYB18TC1G800BF 参数 Datasheet PDF下载

HYB18TC1G800BF图片预览
型号: HYB18TC1G800BF
PDF下载: 下载PDF文件 查看货源
内容描述: 1千兆位双数据速率- SDRAM双 [1-Gbit Double-Data-Rate-Two SDRAM]
分类和应用: 动态存储器
文件页数/大小: 65 页 / 3555 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYB18TC1G[80/16]0BF  
1-Gbit Double-Data-Rate-Two SDRAM  
7.4  
ODT AC Electrical Characteristics  
This chapter describes the ODT AC electrical characteristics.  
TABLE 55  
ODT AC Characteristics and Operating Conditions for DDR2-667 & DDR2-800  
Symbol  
Parameter / Condition  
Values  
Unit  
Note  
Min.  
Max.  
1)  
tAOND  
tAON  
ODT turn-on delay  
2
2
nCK  
ns  
1)2)  
1)  
ODT turn-on  
tAC.MIN  
tAC.MAX + 0.7 ns  
tAONPD  
tAOFD  
tAOF  
ODT turn-on (Power-Down Modes)  
ODT turn-off delay  
t
AC.MIN + 2 ns  
2 tCK +  
t
AC.MAX + 1 ns  
ns  
1)  
2.5  
2.5  
nCK  
ns  
1)3)  
1)  
ODT turn-off  
tAC.MIN  
tAC.MAX + 0.6 ns  
tAOFPD  
tANPD  
tAXPD  
ODT turn-off (Power-Down Modes)  
ODT to Power Down Mode Entry Latency  
ODT Power Down Exit Latency  
t
AC.MIN + 2 ns  
2.5 tCK +  
tAC.MAX + 1 ns  
ns  
1)  
3
8
nCK  
nCK  
1)  
1) New units, “tCK.AVG” and “nCK”, are introduced in DDR2-667 and DDR2-800. Unit “tCK.AVG” represents the actual tCK.AVG of the input clock  
under operation. Unit “nCK” represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and  
DDR2-533, “tCK” is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may  
be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min)  
.
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the  
ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-667/800, tAOND is 2 clock  
cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.  
3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.  
Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-667/800, if tCK(avg) = 3 ns is assumed, tAOFD is 1.5  
ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the  
actual input clock edges.  
Rev. 1.21, 2007-07  
56  
02282007-F8UP-4HSU