Internet Data Sheet
HYB18T512161B2F–20/25
512-Mbit Double-Data-Rate-Two SDRAM
12) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
13) The Auto-Refresh command interval has be reduced to 3.9 μs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
14) 0 °C ≤ TCASE ≤ 85 °C
15) 85 °C < TCASE ≤ 95 °C
16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
17) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
18) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
19) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
5.7.3
ODT AC Electrical Characteristics
TABLE 30
ODT AC Electrical Characteristics and Operating Conditions for all bins
Symbol
Parameter / Condition
Values
Unit Note
Min.
Max.
tAOND
tAON
ODT turn-on delay
2
2
tCK
1)
ODT turn-on
tAC.MIN
t
AC.MAX + 0.7 ns
ns
tAONPD
tAOFD
tAOF
ODT turn-on (Power-Down Modes)
ODT turn-off delay
t
AC.MIN + 2 ns
2 tCK +
t
AC.MAX + 1 ns
ns
2.5
2.5
tCK
2)
ODT turn-off
tAC.MIN
t
AC.MAX + 0.6 ns
ns
tAOFPD
tANPD
tAXPD
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
t
AC.MIN + 2 ns
2.5 tCK + tAC.MAX + 1 ns ns
3
8
—
—
tCK
tCK
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measure from tAOND
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
.
Both are measured from tAOFD
.
Rev. 1.1, 2007-06
28
05152007-ZYAH-ACMZ
Date: 2008-02-26
QIMONDA [ QIMONDA AG ]
