Internet Data Sheet
HYB18T512161B2F–20/25
512-Mbit Double-Data-Rate-Two SDRAM
5.7
AC Characteristics
5.7.1
Speed Grade Definitions
TABLE 28
Speed Grade Definition
Speed Grade
–20
–25
Unit
Note
Parameter
Symbol
Min.
Max.
Min.
Max.
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
@ CL = 6
@ CL = 7
tCK
tCK
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
5
8
5
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.75
3
8
3.75
3
8
8
8
2.5
2.0
45
60
15
15
8
2.5
—
45
60
15
15
8
8
—
70k
—
—
—
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
70k
—
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other Slew Rates see Chapter 8Timings
are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the “Reference Load for Timing Measurements” according
to Chapter 7.1 only.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, input reference
level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS is defined in
Chapter 7.3.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT. See Chapter 7.1 for the reference load for timing measurements.
5)
tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
Rev. 1.1, 2007-06
25
05152007-ZYAH-ACMZ
Date: 2008-02-26
QIMONDA [ QIMONDA AG ]
