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HYB18T512161B2F-25 参数 Datasheet PDF下载

HYB18T512161B2F-25图片预览
型号: HYB18T512161B2F-25
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 32MX16, 0.5ns, CMOS, PBGA84, ROHS COMPLIANT, PLASTIC, TFBGA-84]
分类和应用: 时钟动态存储器双倍数据速率内存集成电路
文件页数/大小: 37 页 / 1297 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYB18T512161B2F–20/25  
512-Mbit Double-Data-Rate-Two SDRAM  
5.7.2  
AC Timing Parameters  
List of Timing Parameters  
TABLE 29  
Timing Parameter by Speed Grade  
Parameter  
Symbol –20  
Min.  
–25  
Unit Notes1)  
2)3)4)5)6)  
Max.  
Min.  
Max.  
DQ output access time from CK / CK  
CAS A to CAS B command period  
CK, CK high-level width  
tAC  
–450  
2
+450  
–500  
2
+500  
ps  
tCCD  
tCH  
tCKE  
tCL  
tCK  
tCK  
tCK  
tCK  
0.45  
3
0.55  
0.45  
3
0.55  
CKE minimum high and low pulse width  
CK, CK low-level width  
0.45  
WR + tRP  
0.55  
0.45  
WR + tRP  
0.55  
7)18)  
Auto-Precharge write recovery + precharge  
time  
tDAL  
tCK  
8)  
Minimum time clocks remain ON after CKE  
asynchronously drops LOW  
tDELAY  
tDH  
tIS + tCK + tIH ––  
tIS + tCK + tIH ––  
ns  
9)  
DQ and DM input hold time (differential data  
strobe)  
145  
––  
––  
250  
0
––  
––  
ps  
9)  
DQ and DM input hold time (single ended data tDH1  
-105  
ps  
strobe)  
DQ and DM input pulse width (each input)  
DQS output access time from CK / CK  
tDIPW  
0.35  
–450  
0.35  
0.35  
–500  
0.35  
tCK  
9)  
tDQSCK  
+450  
+500  
ps  
DQS input low (high) pulse width (write cycle) tDQSL,H  
tCK  
10)  
DQS-DQ skew (for DQS & associated DQ  
signals)  
tDQSQ  
280  
280  
ps  
Write command to 1st DQS latching transition tDQSS  
WL – 0.25  
20  
WL +  
0.25  
WL – 0.25  
WL +  
0.25  
tCK  
9)  
DQ and DM input setup time (differential data tDS  
strobe)  
125  
0
––  
ps  
9)  
DQ and DM input setup time (single ended data tDS1  
-105  
––  
ps  
strobe)  
DQS falling edge hold time from CK (write cycle) tDSH  
DQS falling edge to CK setup time (write cycle) tDSS  
0.2  
0.2  
0.2  
0.2  
tCK  
tCK  
11)  
Clock half period  
tHP  
tHZ  
tIH  
MIN. (tCL,  
t
CH) —  
MIN. (tCL,  
t
CH) —  
tAC.MAX ps  
12)  
Data-out high-impedance time from CK / CK  
Address and control input hold time  
tAC.MAX  
525  
575  
ps  
Address and control input pulse width  
(each input)  
tIPW  
0.6  
0.6  
tCK  
Address and control input setup time  
DQ low-impedance time from CK / CK  
tIS  
400  
450  
ps  
12)  
12)  
tLZ(DQ)  
2 ×  
tAC.MIN  
tAC.MAX  
2 ×  
tAC.MIN  
tAC.MAX ps  
DQS low-impedance from CK / CK  
tLZ(DQS)  
tMRD  
tAC.MIN  
tAC.MAX tAC.MIN  
tAC.MAX ps  
tCK  
Mode register set command cycle time  
2
2
Rev. 1.1, 2007-06  
26  
05152007-ZYAH-ACMZ  
Date: 2008-02-26  
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