U
HJ
ꢌꢀ
D
G
G
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Zꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Zꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Zꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Zꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ZꢀꢀꢀꢀꢀꢀꢀꢀZ
ꢀꢀꢀꢀꢀꢀꢀꢀZ
ꢀꢀꢀꢀꢀꢀꢀ
Internet Data Sheet
HYB18T512161BF–20/22/25/28/33
512-Mbit Double-Data-Rate-Two SDRAM
%
$ꢂ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ%
$
ꢁ
ꢀꢀꢀꢀꢀꢀꢀ
$
ꢂ
ꢃ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀ
$
ꢂ
ꢁ
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ꢈ
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&ꢀ'ꢀꢀꢀ
ꢇ
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ꢆ
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ꢄ
ꢀꢀꢀꢀꢀꢀ$
ꢊ
ꢀꢀꢀꢀꢀꢀ$
ꢉ
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ꢅ
ꢀꢀꢀꢀꢀꢀ$
ꢃ
ꢀꢀꢀꢀꢀꢀ$
ꢂ
ꢀꢀꢀꢀꢀꢀ$
ꢁ
ꢀꢀꢀꢀꢀꢀ
$
ꢂ
ꢂ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
4ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
Iꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢁꢀ
2
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3
U
R
J
U
DP
ꢀꢀꢀꢀꢀꢀꢀꢀꢀ
'4
6
5ꢀWꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
$
/ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 5ꢀWꢀꢀꢀꢀꢀꢀꢀ'
,
&
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ'ꢀ/
/
ꢀꢀꢀꢀꢀꢀ
ꢁꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢂ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀRI
Wꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
Wꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
TABLE 7
Extended Mode Register Definition (BA[1:0] = 01B)
Field
Bits
Type1)
Description
Bank Address [1]
BA1
14
reg. addr.
0B
BA1 Bank Address
BA0
Qoff
13
12
Bank Address [0]
0B
BA0 Bank Address
w
Output Disable
0B
1B
QOff Output buffers enabled
QOff Output buffers disabled
DQS
10
Complement Data Strobe (DQS Output)
0B
1B
DQS Enable
DQS Disable
OCD
Program
[9:7]
Off-Chip Driver Calibration Program
000B OCD OCD calibration mode exit, maintain setting
001B OCD Drive (1)
010B OCD Drive (0)
100B OCD Adjust mode
111B OCD OCD calibration default
AL
[5:3]
Additive Latency
Note: All other bit combinations are illegal.
000B AL 0
001B AL 1
010B AL 2
011B AL 3
100B AL 4
101B AL 5
110B AL 6
RTT
2,6
Nominal Termination Resistance of ODT
00B RTT ∞ (ODT disabled)
01B RTT 75 Ohm
10B RTT 150 Ohm
11B RTT 50 Ohm
DIC
DLL
1
0
Off-chip Driver Impedance Control
0B
1B
DIC Full (Driver Size = 100%)
DIC Reduced
DLL Enable
0B
1B
DLL Enable
DLL Disable
1) w = write only register bits
Rev. 1.43, 2006-11
12
03292006-L40N-L04G
QIMONDA [ QIMONDA AG ]
