Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
Parameter
Symbol DDR2–800
Min.
DDR2–667
Unit
Note1)2)3
)4)5)6)7)
Max.
Min.
Max.
Mode register set command cycle
time
tMRD
2
—
2
—
nCK
34)
OCD drive mode output delay
tOIT
0
12
0
12
ns
ps
ps
μs
μs
ns
25)
DQ/DQS output hold time from DQS tQH
t
HP – tQHS
—
t
HP – tQHS
—
26)
DQ hold skew factor
tQHS
tREFI
—
—
—
75
300
7.8
3.9
—
—
—
—
75
340
7.8
3.9
—
27)28)
27)29)
30)
Average periodic refresh Interval
Auto-Refresh to Active/Auto-Refresh tRFC
command period
31)32)
31)33)
34)
Read preamble
Read postamble
tRPRE
tRPST
0.9
0.4
7.5
1.1
0.6
—
0.9
0.4
7.5
1.1
0.6
—
tCK.AVG
tCK.AVG
ns
Active to active command period for tRRD
1KB page size products
34)
Internal Read to Precharge command tRTP
7.5
—
7.5
—
ns
delay
Write preamble
tWPRE
tWPST
tWR
0.35
0.4
—
0.6
—
—
—
—
0.35
0.4
—
0.6
—
—
—
—
tCK.AVG
tCK.AVG
ns
Write postamble
Write recovery time
34)
15
15
34)35)
Internal write to read command delay tWTR
Exit power down to read command tXARD
7.5
7.5
ns
2
2
nCK
nCK
Exit active power-down mode to read tXARDS
8 – AL
7 – AL
command (slow exit, lower power)
Exit precharge power-down to any
valid command (other than NOP or
Deselect)
tXP
2
—
2
—
nCK
ns
34)
Exit self-refresh to a non-read
command
tXSNR
t
RFC +10
—
—
t
RFC +10
—
—
Exit self-refresh to read command
tXSRD
200
200
nCK
nCK
Write command to DQS associated
clock edges
WL
RL – 1
RL–1
1) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V.
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) under the Reference Load for Timing Measurements.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
6) The output timing reference voltage level is VTT.
7) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min)
.
Rev. 1.50, 2007-12
42
03062006-7M17-PXBC
QIMONDA [ QIMONDA AG ]
