Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
7.2
Component AC Timing Parameters
TABLE 38
DRAM Component Timing Parameter by Speed Grade - DDR2–800 and DDR2–667
Parameter
Symbol DDR2–800
DDR2–667
Unit
Note1)2)3
)4)5)6)7)
Min.
Max.
Min.
Max.
8)
DQ output access time from CK / CK tAC
–400
2
+400
—
–450
2
+450
—
ps
CAS to CAS command delay
Average clock high pulse width
Average clock period
tCCD
tCH.AVG
tCK.AVG
nCK
tCK.AVG
ps
9)10)
11)
0.48
2500
3
0.52
8000
—
0.48
3000
3
0.52
8000
—
CKE minimum pulse width ( high and tCKE
nCK
low pulse width)
9)10)
Average clock low pulse width
tCL.AVG
tDAL
0.48
0.52
—
0.48
0.52
—
tCK.AVG
12)13)
Auto-Precharge write recovery +
precharge time
WR + tnRP
WR + tnRP
nCK
Minimum time clocks remain ON after tDELAY
CKE asynchronously drops LOW
tIS + tCK .AVG ––
+ tIH
tIS +
tCK .AVG + tIH
––
ns
14)18)19)
DQ and DM input hold time
tDH.BASE
125
––
—
175
––
—
ps
DQ and DM input pulse width for each tDIPW
0.35
0.35
tCK.AVG
input
8)
DQS output access time from CK / CK tDQSCK
–350
0.35
0.35
—
+350
—
–400
0.35
0.35
—
+400
—
ps
DQS input high pulse width
DQS input low pulse width
tDQSH
tDQSL
tCK.AVG
tCK.AVG
ps
—
—
15)
16)
DQS-DQ skew for DQS & associated tDQSQ
DQ signals
200
240
DQS latching rising transition to
associated clock edges
tDQSS
– 0.25
+ 0.25
– 0.25
+ 0.25
tCK.AVG
17)18)19)
16)
DQ and DM input setup time
tDS.BASE
50
––
—
—
__
100
––
—
—
__
ps
DQS falling edge hold time from CK tDSH
0.2
0.2
tCK.AVG
tCK.AVG
ps
16)
DQS falling edge to CK setup time
CK half pulse width
tDSS
tHP
0.2
0.2
20)
Min(tCH.ABS
,
Min(tCH.ABS,
tCL.ABS
)
tCL.ABS)
8)21)
Data-out high-impedance time from tHZ
CK / CK
—
tAC.MAX
—
tAC.MAX
ps
22)24)
Address and control input hold time tIH.BASE
250
0.6
—
—
275
0.6
—
—
ps
Control & address input pulse width tIPW
tCK.AVG
for each input
23)24)
8)21)
8)21)
Address and control input setup time tIS.BASE
DQ low impedance time from CK/CK tLZ.DQ
175
—
200
—
ps
ps
ps
2 x tAC.MIN
tAC.MAX
tAC.MAX
2 x tAC.MIN
tAC.MAX
tAC.MAX
DQS/DQS low-impedance time from tLZ.DQS
tAC.MIN
tAC.MIN
CK / CK
34)
MRS command to ODT update delay tMOD
0
12
0
12
ns
Rev. 1.50, 2007-12
41
03062006-7M17-PXBC
QIMONDA [ QIMONDA AG ]
