Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
TABLE 39
DRAM Component Timing Parameter by Speed Grade - DDR2–533 and DDR2–400
Parameter
Symbol
DDR2–533
DDR2–400
Unit
Notes1)2)
3)4)5)6)
Min.
Max.
Min.
Max.
DQ output access time from CK / CK tAC
CAS A to CAS B command period tCCD
–500
2
+500
—
–600
2
+600
—
ps
tCK
tCK
tCK
CK, CK high-level width
tCH
0.45
3
0.55
—
0.45
3
0.55
—
CKE minimum high and low pulse
width
tCKE
CK, CK low-level width
tCL
0.45
0.55
—
0.45
0.55
—
tCK
tCK
7)
8)
Auto-Precharge write recovery +
precharge time
tDAL
WR + tRP
WR + tRP
Minimum time clocks remain ON
after CKE asynchronously drops
LOW
tDELAY
tIS + tCK + tIH ––
tIS + tCK + tIH ––
ns
9)
DQ and DM input hold time
(differential data strobe)
tDH.BASE
225
–25
0.35
–450
0.35
0.35
—
––
275
25
––
ps
ps
tCK
ps
tCK
tCK
ps
tCK
ps
ps
tCK
tCK
10)
DQ and DM input hold time (single tDH1.BASE
ended data strobe)
—
—
DQ and DM input pulse width (each tDIPW
input)
—
0.35
–500
0.35
0.35
—
—
DQS output access time from CK / tDQSCK
CK
+450
—
+500
—
DQS input HIGH pulse width (write tDQSH
cycle)
DQS input LOW pulse width (write tDQSL
cycle)
—
—
10)
DQS-DQ skew (for DQS &
associated DQ signals)
tDQSQ
300
+ 0.25
—
350
+ 0.25
—
Write command to 1st DQS latching tDQSS
transition
– 0.25
100
–25
0.2
– 0.25
150
25
10)
10)
DQ and DM input setup time
(differential data strobe)
tDS.BASE
DQ and DM input setup time (single tDS1.BASE
ended data strobe)
—
—
DQS falling edge hold time from CK tDSH
(write cycle)
—
0.2
—
DQS falling edge to CK setup time tDSS
0.2
—
0.2
—
(write cycle)
11)
12)
Clock half period
tHP
MIN. (tCL, tCH
)
MIN. (tCL, tCH)
Data-out high-impedance time from tHZ
CK / CK
—
tAC.MAX
—
tAC.MAX
ps
ps
10)
Address and control input hold time tIH.BASE
375
—
475
—
Rev. 1.50, 2007-12
45
03062006-7M17-PXBC
QIMONDA [ QIMONDA AG ]
