Internet Data Sheet
HY[B/I]18T256[40/80/16]0A[C/F](L)
256-Mbit Double-Data-Rate-Two SDRAM
TABLE 37
Speed Grade Definition
Speed Grade
DDR2–667C
–3
DDR2–667D
–3S
DDR2–533C
DDR2–400B Unit Note
QAG Sort Name
CAS-RCD-RP latencies
Parameter
–3.7
–5
4–4–4
5–5–5
4–4–4
Min.
3–3–3
Min.
tCK
Symbol Min.
Max.
Min.
Max.
Max.
Max.
—
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Period @ CL = 3
@ CL = 4
tCK
5
8
5
8
5
8
5
8
ns
ns
ns
ns
ns
ns
ns
tCK
3
8
3.75
3
8
3.75
3.75
45
8
5
8
@ CL = 5
tCK
3
8
8
8
5
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRC
tRCD
tRP
45
57
12
12
70k
—
—
—
45
60
15
15
70k
—
—
—
70k
—
—
—
40
55
15
15
70k
—
—
—
60
15
15
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) .
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode. .
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI
.
Rev. 1.50, 2007-12
40
03062006-7M17-PXBC
QIMONDA [ QIMONDA AG ]
