Internet Data Sheet
HY[B/I]18T1G[40/80/16]0C2[C/F]
1-Gbit Double-Data-Rate-Two SDRAM
3.3
Extended Mode Register EMR(2)
The Extended Mode Registers EMR(2) and EMR(3) are reserved for future use and must be programmed when setting the
mode register during initialization.
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$ꢇ
$ꢊ
$ꢅ
$ꢈ
$ꢁ
ꢀ
$ꢉ
$ꢄ
$ꢆ
$ꢂ
$ꢀ
ꢀ
ꢂ
ꢀ
ꢀ
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TABLE 13
EMR(2) Programming Extended Mode Register Definition, BA2:0=010B
Field Bits
Type1)
Description
BA2
16
w
Bank Address
Note: BA2 is not available on 256 Mbit and 512 Mbit components
0B
BA2 Bank Address
BA
[15:14]
w
Bank Adress
00B BA MRS
01B BA EMRS(1)
10B BA EMRS(2)
11B BA EMRS(3): Reserved
A
[13:8]
7
w
w
Address Bus
000000B A Address bits
SRF
Address Bus, High Temperature Self Refresh Rate for TCASE > 85°C
0B
1B
A7 disable
A7 enable 2)
A
[6:4]
3
w
w
Address Bus
000B A Address bits
DCC
Address Bus, Duty Cycle Correction (DCC)
0B
1B
A3 DCC disabled
A3 DCC enabled
Partial Self Refresh for 8 banks
PASR [2:0]
w
Address Bus, Partial Array Self Refresh for 8 Banks3)
Note: Only for 1G and 2G components
000B PASR0 Full Array
001B PASR1 Half Array (BA[2:0]=000, 001, 010 & 011)
010B PASR2 Quarter Array (BA[2:0]=000, 001)
011B PASR3 1/8 array (BA[2:0] = 000)
100B PASR4 3/4 array (BA[2:0]= 010, 011, 100, 101, 110 & 111)
101B PASR5 Half array (BA[2:0]=100, 101, 110 & 111)
110B PASR6 Quarter array (BA[2:0]= 110 & 111)
111B PASR7 1/8 array(BA[2:0]=111)
1) w = write only
2) When DRAM is operated at 85°C ≤ TCase ≤ 95°C the extended self refresh rate must be enabled by setting bit A7 to 1 before the self refresh
mode can be entered.
Rev. 1.02, 2008-01
24
09262007-3YK7-BKKG
QIMONDA [ QIMONDA AG ]
