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Internet Data Sheet
HY[B/I]18T1G[40/80/16]0C2[C/F]
1-Gbit Double-Data-Rate-Two SDRAM
3.2
Extended Mode Register EMR(1)
The Extended Mode Register EMR(1) stores the data for
enabling or disabling the DLL, output driver strength, additive
latency, OCD program, ODT, DQS and output buffers
disable, RDQS and RDQS enable.
%
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$
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$
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TABLE 12
Extended Mode Register Definition, BA2:0 = 001B
Field
Bits Type1)
Description
Bank Address 2
Note: BA2 not available on 256 Mbit and 512 Mbit components
0B BA2 Bank Address
Bank Address 1
BA2
16
reg. addr.
BA1
BA0
A13
Qoff
15
14
13
12
0B
BA1 Bank Address
Bank Address 0
1B
BA0 Bank Address
w
w
Address Bus
0B
A13 Address bit 13
Output Disable
0B
1B
QOff Output buffers enabled
QOff Output buffers disabled
RDQS
DQS
11
w
w
w
Read Data Strobe Output (RDQS, RDQS)
0B
1B
RDQS Disable
RDQS Enable
10
Complement Data Strobe (DQS Output)
0B
1B
DQS Enable
DQS Disable
OCD
Program
[9:7]
Off-Chip Driver Calibration Program
000B OCD OCD calibration mode exit, maintain setting
001B OCD Drive (1)
010B OCD Drive (0)
100B OCD Adjust mode
111B OCD OCD calibration default
AL
[5:3]
w
Additive Latency
Note: All other bit combinations are illegal.
000B AL 0
001B AL 1
010B AL 2
011B AL 3
100B AL 4
Rev. 1.02, 2008-01
22
09262007-3YK7-BKKG
QIMONDA [ QIMONDA AG ]
