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Internet Data Sheet
HY[B/I]18T1G[40/80/16]0C2[C/F]
1-Gbit Double-Data-Rate-Two SDRAM
3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refresh
is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued.
3.4
Extended Mode Register EMR(3)
The Extended Mode Register EMR(3) is reserved for future use and all bits except BA0 and BA1 must be programmed to 0
when setting the mode register during initialization.
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TABLE 14
EMR(3) Programming Extended Mode Register Definition, BA2:0=011B
Field
Bits
Type1)
Description
BA2
16
reg.addr
Bank Address 2
Note: BA2 is not available on 256Mbit and 512Mbit components
0B
BA2 Bank Address
BA1
BA0
A
15
Bank Adress 1
1B
BA1 Bank Address
14
Bank Adress 0
1B
BA0 Bank Address
[13:0]
w
Address Bus 13:0
00000000000000BA[13:0] Address bits
1) w = write only
Rev. 1.02, 2008-01
25
09262007-3YK7-BKKG
QIMONDA [ QIMONDA AG ]
