Internet Data Sheet
HY[B/I]18T1G[40/80/16]0C2[C/F]
1-Gbit Double-Data-Rate-Two SDRAM
3
Functional Description
This chapter contains the functional description.
3.1
Mode Register Set (MRS)
The mode register stores the data for controlling the various
operating modes of DDR2 SDRAM.
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TABLE 11
Mode Register Definition, BA2:0 = 000B
Field
Bits
Type1)
Description
BA2
16
reg. addr.
Bank Address 2
Note: BA2 not available on 256 Mbit and 512 Mbit components
0B BA2 Bank Address
Bank Address 1
BA1
BA0
A13
PD
15
14
13
12
0B
BA1 Bank Address
Bank Address 0
0B
BA0 Bank Address
Address Bus
0B
A13 Address bit 13
w
w
Active Power-Down Mode Select
0B
1B
PD Fast exit
PD Slow exit
WR
[11:9]
Write Recovery2)
Note: All other bit combinations are illegal.
001B WR 2
010B WR 3
011B WR 4
100B WR 5
101B WR 6
DLL
TM
8
7
w
w
DLL Reset
0B
1B
DLL No
DLL Yes
Test Mode
0B
1B
TM Normal Mode
TM Vendor specific test mode
Rev. 1.02, 2008-01
20
09262007-3YK7-BKKG
QIMONDA [ QIMONDA AG ]
