HYB18T1G[40/80/16]0AF(L)–[3S/3.7/5]
1-Gbit DDR2 SDRAM
Timing Characteristics
Table 36
Timing Parameter by Speed Grade - DDR2–667 (cont’d)
Parameter
Symbol
DDR2–667
Unit
Note1)2)3)4)5)6)
Min.
Max.
12
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
tOIT
0
ns
tQH
t
HPQ – tQHS
—
tQHS
tREFI
—
—
340
7.8
3.9
—
ps
µs
µs
ns
15)16)
17)
Average periodic refresh Interval
—
18)
Auto-Refresh to Active/Auto-Refresh
command period
tRFC
127.5
Read preamble
Read postamble
tRPRE
tRPST
tRRD
0.9
1.1
0.60
—
tCK
tCK
ns
ns
ns
tCK
tCK
ns
0.40
7.5
19)
22)
Active bank A to Active bank B command
period
10
—
Internal Read to Precharge command delay tRTP
7.5
—
Write preamble
Write postamble
tWPRE
tWPST
tWR
0.35 x tCK
0.40
15
—
20)
21)
0.60
—
Write recovery time for write without Auto-
Precharge
Write recovery time for write with Auto-
Precharge
WR
t
WR/tCK
tCK
22)
23)
Internal Write to Read command delay
tWTR
7.5
2
—
—
ns
Exit power down to any valid command
(other than NOP or Deselect)
tXARD
tCK
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
tXP
7 – AL
2
—
—
tCK
tCK
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
1) VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1 V. See notes 6)7)
tXSNR
tXSRD
t
RFC +10
—
—
ns
200
tCK
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
powered down and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are
further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross.
The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
6) The output timing reference voltage level is VTT.
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period.
WR refers to the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock
frequency change during power-down, a specific procedure is required.
9) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle.
10) ×4 & ×8 (1k page size)
Internet Data Sheet
38
Rev. 1.31, 2007-01
03292006-1X3H-6X8S
QIMONDA [ QIMONDA AG ]
