Internet Data Sheet
HY[B/E]18M256[16/32]0CF
256-Mbit DDR Mobile-RAM
3.3
Operating Currents
TABLE 13
Maximum Operating Currents
Parameter & Test Conditions
Symbol
Values
Unit Note
1)2)3)4)5)
– 6
– 7.5
Operating one bank active-precharge current:
IDD0
45 (x16)
60 (x32)
40 (x16)
55 (x32)
mA
t
RC = tRCmin; tCK = tCKmin; CKE is HIGH; CS is HIGH between valid
commands; address inputs are SWITCHING; data bus inputs are
STABLE
Precharge power-down standby current:
All banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin; address and control
inputs are SWITCHING; data bus inputs are STABLE
IDD2P
0.7
0.3
15
8
0.7
0.3
15
8
mA
mA
mA
mA
mA
mA
mA
mA
Precharge power-down standby current with clock stop:
All banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address
and control inputs are SWITCHING; data bus inputs are STABLE
IDD2PS
IDD2N
IDD2NS
IDD3P
Precharge non power-down standby current:
All banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin;address and control
inputs are SWITCHING; data bus inputs are STABLE
Precharge non power-down standby current with clock stop:
All banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;address
and control inputs are SWITCHING; data bus inputs are STABLE
Active power-down standby current:
One bank active, CKE is LOW; CS is HIGH, tCK = tCKmin; address and
control inputs are SWITCHING; data bus inputs are STABLE
2.0
1.5
25
20
2.0
1.5
23
20
Active power-down standby current with clock stop:
One bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
IDD3PS
IDD3N
IDD3NS
Active non power-down standby current:
One bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin;address and
control inputs are SWITCHING; data bus inputs are STABLE
Active non power-down standby current with clock stop:
One bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK =
HIGH;address and control inputs are SWITCHING; data bus inputs are
STABLE
Operating burst read current:
IDD4R
115 (x16) 90 (x16)
140 (x32) 110 (x32)
mA
One bank active; BL = 4; CL = 3; tCK = tCKmin; continuous read bursts; IOUT
= 0 mAaddress inputs are SWITCHING; 50% data change each burst
transfer
Operating burst write current:
One bank active; BL = 4; tCK = tCKmin; continuous write bursts; address
inputs are SWITCHING; 50% data change each burst transfer
IDD4W
110 (x16) 85 (x16)
115 (x32) 90 (x32)
mA
mA
Auto-Refresh current:
IDD5
75 (x16)
70 (x16)
t
RC = tRFCmin; tCK = tCKmin; burst refresh; address and control inputs are
120 (x32) 110 (x32)
SWITCHING; data bus inputs are STABLE
Rev.1.44, 2007-07
19
06262007-JK8G-48BV
QIMONDA [ QIMONDA AG ]
