Internet Data Sheet
HY[B/E]18M256[16/32]0CF
256-Mbit DDR Mobile-RAM
3.2
AC Characteristics
TABLE 11
AC Characteristics
Parameter
Symbol
– 6
– 7.5
Unit Note
1)2)3)4)
Min.
2.0
Max.
5.5
5.5
Min.
2.5
Max.
5)6)
DQ output access time from CK/CK
DQS output access time from CK/CK
Clock high-level width
tAC
6.0
6.0
ns
5)6)
tDQSCK
tCH
2.0
2.5
ns
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
tCK
tCK
ns
ns
–
Clock low-level width
tCL
–
7)8)
Clock half period
tHP
min(tCL, tCH
)
min(tCL, tCH)
Clock cycle time
CL = 3
tCK
6
–
7.5
12
–
CL = 2
12
0.6
0.7
0.6
0.7
1.5
1.1
1.3
1.1
1.3
2.6
1.0
–
–
–
9)10)11)
9)10)12)
9)10)12)
9)10)13)
13)
DQ and DM input
Setup time
fast slew rate
slow slew rate
tDS
–
0.75
0.85
0.75
0.85
1.7
1.3
1.5
1.3
1.5
3.0
1.0
–
–
ns
ns
–
–
DQ and DM input
hold time
Fast slew rate tDH
–
–
Slow slew rate
–
–
DQ and DM input pulse width
tDIPW
tIS
–
–
ns
ns
12)14)15)
13)15)16)
12)15)16)
13)15)16)
14)
Address and control input
Setup time
fast slew rate
slow slew rate
fast slew rate
slow slew rate
–
–
–
–
Address and control input
hold time
tIH
–
–
ns
–
–
Address and control input pulse width
DQ & DQS low-impedance time from CK/CK
DQ & DQS high-impedance time from CK/CK
DQS - DQ skew
tIPW
–
–
ns
16)
tLZ
–
–
ns
17)
tHZ
5.5
0.5
–
6.0
0.6
–
ns
17)
tDQSQ
tQH
–
–
ns
8)
DQ / DQS output hold time from DQS
Data hold skew factor
t
HP-tQHS
tHP-tQHS
ns
8)
tQHS
tDQSS
tDQSH
tDQSL
tDSC
–
0.55
1.25
0.6
0.6
1.1
–
–
0.75
1.25
0.6
0.6
1.1
–
ns
Write command to 1st DQS latching transition
DQS input high-level width
0.75
0.4
0.4
0.9
0.2
0.2
2
0.75
0.4
0.4
0.9
0.2
0.2
2
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
–
–
–
–
–
–
DQS input low-level width
DQS input cycle time
DQS falling edge to CK setup time
DQS falling edge hold time from CK
MODE REGISTER SET command period
Write preamble setup time
tDSS
tDSH
–
–
tMRD
tWPRES
tWPREH
tWPST
tWPRE
–
–
–
18)
0
–
0
–
Write preamble hold time
0.25
0.4
0.25
–
0.25
0.4
0.25
–
tCK
tCK
tCK
–
19)
Write postamble
0.6
–
0.6
–
Write preamble
–
Rev.1.44, 2007-07
16
06262007-JK8G-48BV
QIMONDA [ QIMONDA AG ]
