Internet Data Sheet
HY[B/E]18M256[16/32]0CF
256-Mbit DDR Mobile-RAM
Parameter
Symbol
– 6
– 7.5
Unit Note
1)2)3)4)
Min.
0.9
Max.
1.1
Min.
0.9
Max.
20)
Read preamble
Read postamble
CL = 3
CL = 2
tRPRE
1.1
1.1
0.6
tCK
–
–
0.5
0.4
45
tRPST
tRAS
tRC
0.4
42
60
72
0.6
tCK
ns
ns
ns
–
21)
ACTIVE to PRECHARGE command period
ACTIVE to ACTIVE command period
70k
–
70k
–
22)
22)
67
AUTO REFRESH to ACTIVE/AUTO REFRESH
command period
tRFC
–
75
–
22)
ACTIVE to READ or WRITE delay
Col address to col address delay
PRECHARGE command period
ACTIVE bank A to ACTIVE bank B delay
WRITE recovery time
tRCD
tCCD
tRP
18
1
–
–
–
–
–
22.5
1
–
–
–
–
–
ns
tCK
ns
ns
ns
tCK
tCK
ns
ns
tCK
ms
22)
22)
22)
22)
23)
22)
18
12
15
22.5
15
tRRD
tWR
15
Auto precharge write recovery + precharge time
Internal write to Read command delay
Self refresh exit to next valid command delay
Exit power down delay
tDAL
tWTR
tXSR
tXP
(tWR/tCK) + (tRP/tCK)
1
–
1
–
120
–
120
–
t
CK + tIS
–
tCK + tIS
–
–
–
CKE minimum low time
tCKE
tREF
tREFI
2
–
–
–
2
–
–
–
Refresh period
64
64
24)
Average periodic refresh interval
7.8 (× 16)
15.6 (x32)
7.8 (× 16) µs
15.6 (x32)
1) 0 °C ≤ TC ≤ 70 °C (comm.); -25°C ≤ TC ≤ 85 °C (ext.);VDD = 1.70 V - 1.95 V, VDDQ = 1.70 V - 1.95 V. All voltages referenced to VSS
.
2) All parameters assume proper device initialization.
3) The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK; the input reference level for signals
other than CK/CK is VDDQ/2.
4) All AC timing characteristics assume an input slew rate of 1.0 V/ns.
5) The output timing reference level is VDDQ/2.
6) Parameters tAC and tQH are specified for full drive strength and a reference load see Figure 3. This circuit is not intended to be either a
precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. For half drive
strength with a nominal load of 10pF parameters tAC and tQH are expected to be in the same range. However, these parameters are not
subject to production test but are estimated by device characterization. Use of IBIS or other simulation tools for system validation is
suggested.
7) Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
8)
tQH = tHP - tQHS, where tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCL, tCH). tQHS accounts
for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one transition followed by the worst
case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to
n-channel variation of the output drivers.
9) DQ, DM and DQS input slew rate is measured between VILD(DC) and VIHD(AC) (rising) or VIHD(DC) and VILD(AC) (falling).
10) DQ, DM and DQS input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions
through the DC region must be monotonic.
11) Input slew rate ≥ 1.0 V/ns.
12) Input slew rate ≥ 0.5V/ns and < 1.0 V/ns.
13) These parameters guarantee device timing. They are verified by device characterization but are not subject to production test.
14) The transition time for address and command inputs is measured between VIH and VIL.
15) A CK/CK differential slew rate of 2.0 V/ns is assumed for this parameter.
16) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
Rev.1.44, 2007-07
17
06262007-JK8G-48BV
QIMONDA [ QIMONDA AG ]
