HYB18H512321AF
512-Mbit GDDR3
Functional Description
0
1
2
3
6
7
8
9
10
11
12
13
CLK#
CLK
Com.
Addr.
RD
DES
DES
DES
DES
DES
WR
DES
DES
DES
DES
DES
B/Cr
B/Cw
CAS latency = 7
tRTW
tDQSCKOFF
RDQS
WDQS
DQ
Write latency = 3
D0r D1r D2r D3r
D0w D1w D2w D0w
tACOFF
RD
DES
DES
DES
DES
DES
WR
DES
DES
DES
DES
DES
B/Cr
B/Cw
CAS latency = 8
tRTW
tDQSCKOFF
RDQS
WDQS
Write latency = 4
DQ
D0r D1r
D2r D3r
D0w D1w D2w
tACOFF
B / Cr: Bank / Column address for READ
B / Cw: Bank / Column address for WRITE
Dxr:
READ Data from B / C
Don't Care
Dxw: WRITE Data from B / C
Com.: Command
DQs : Terminations off
RDQS : Not driven
RD:
READ
WR:
WRITE
Addr.: Address B / C
DES: Deselect
Figure 64 DLL off: Read followed by Write
Data Sheet
78
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
