HYB18H512321AF
512-Mbit GDDR3
Functional Description
Table 24
Read Timing Parameter
Parameter
Read
Latency
Symbol
Limit Values
-16
Unit Note
-20
min
max min
max
Read to Write command delay
tRTW
t
RTW(min) = (CL+4-WL)
tCK
Read Cycle Timing Parameters for Data and Data Strobe
Data Access Time from Clock in DLL off mode
DQS edge to Clock edge skew in DLL off mode
tACOFF
tDQSCK
2.4
2.4
6.2
6.2
2.4
2.4
6.2
6.2
ns
ns
0
1
2
3
6
7
8
9
10
CLK#
CLK
Com.
Addr.
RD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
B / C
CAS latency = 7
tDQSCK
RDQS
DQ
D0
D1
D2
D3
tACOFF
CAS latency = 8
tDQSCK
RDQS
DQ
D0
D1
D2
D3
tACOFF
B / C: Bank / Column address
RD:
Dx:
READ
Data from B / C
Com.: Command
Don't Care
Addr.: Address B / C
N/D: NOP or Deselect
Figure 63 DLL off: Read Burst
Data Sheet
77
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
