HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.7.7
Read followed by Write
0
1
2
3
6
7
8
9
10
11
12
13
CLK#
CLK
Com.
RD
DES
DES
DES
DES
DES
WR
DES
DES
DES
DES
DES
Addr.
B/Cr
B/Cw
CAS latency = 7
tRTW
Write latency = 3
RDQS
WDQS
DQ
D0r D1r D2r D3r
D0w D1w D2w D3w
RD
DES
DES
DES
DES
DES
WR
DES
DES
DES
DES
DES
B/Cr
B/Cw
CAS latency = 8
tRTW
Write latency = 4
RDQS
WDQS
DQ
D0r D1r D2r D3r
D0w D1w D2w
Dxr:
READ Data from B / C
B / Cr: Bank / Column address for READ
B / Cw: Bank / Column address for WRITE
Don't Care
Dxw: WRITE Data from B / C
Com.: Command
Addr.: Address B / C
DQs : Terminations off
RDQS : Not driven
RD:
WR:
READ
WRITE
DES: Deselect
Figure 43 Read followed by Write
1. Shown with nominal tAC, tDQSQ and tDQSS
2. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge
of RDQS.
3. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last
Read data
4. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
5. The Write command may be either on the same bank or on another bank.
Data Sheet
62
Rev. 1.73, 2005-08
05122004-B1L1-JEN8
QIMONDA [ QIMONDA AG ]
