HYB18H512321AF
512-Mbit GDDR3
Functional Description
4.7.6
Read with Autoprecharge
0
1
2
3
6
7
8
9
10
CLK#
CLK
Com.
RD/A
B / C
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
A9,
A7-A2
A8
CAS latency = 7
RDQS
DQ
D0
D1
D2
D3
CAS latency = 8
RDQS
DQ
D0
D1
D2
D3
BL / 2
tRP
B / C: Bank / Column address
RD/A: READ with auto-precharge
Dx: Data from B / C
Com.: Command
Addr.: Address B / C
N/D: NOP or Deselect
Don't Care
Begin of
Autoprecharge
DQs : Terminations off
RDQS : Not driven
Figure 42 Read with Autoprecharge
1. When issuing a RD/A command , the tRAS requirement must be met at the beginning of Autoprecharge
2. Shown with nominal tAC and tDQSQ
3. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge
of RDQS.
4. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last
Read data.
5. tRAS Lockout support.
Data Sheet
61
Rev. 1.73, 2005-08
05122004-B1L1-JEN8